The present invention relates to an information processing apparatus in which various kinds of information are processed in either a real time processing mode or a non-real time processing mode, both co-existing in the apparatus, and specifically relates to improvements of processing efficiency and scheduling aspects of a processor provided in the information processing apparatus.
With respect to the conventional image forming apparatus, there has been well-known that, in the case that small-sized jobs in regard to the image forming operation are continuously implemented or the like, the responsivity of the operating section of the image forming apparatus concerned is getting worth. In this connection, in such the conventional image forming apparatus serving as an image production apparatus, although a high-speed depicting GPU (Graphical Processing Unit) is allotted to the operating section, the depiction instruction controlling operation is implemented by employing the main-body single core CPU (Central Processing Unit). When a high-speed image output processing is performed in the abovementioned image production apparatus, there has arisen such a problem that the depicting instruction of the operating section has been delayed due to the waiting time for process transitions caused by the single core CPU, and accordingly, the responsivity of the depiction processing of the operating section, which is allotted as a low priority thread process, is deteriorated.
Further, generally speaking, the operation for processing a job, to be conducted in the normal-type copier, is performed in such a manner that plural processes are performed in parallel and in conjunction with each other. Accordingly, the copier as a whole is constituted by various kinds of modules and circuit boards in which plural CPUs having heterogeneous functions and characteristics, being different form each other, are respectively provided, and a total controlling circuit board in which a main CPU controls the abovementioned plural processes, in such a manner that the total controlling circuit board unifies the plurality of modules and circuit boards.
In the above-configuration of the conventional copier, a plurality of single core CPUs is employed so as to activate the plural processes in parallel by using the thread processing mechanism provided in the OS (Operating System).
For instance, with respect to initialization processing of a plurality of physical media or the like, it has been well-known that the method for employing plural thread processes at a time so as to conduct the initialization processing in parallel, is more speedy rather than the other method for employing a single thread process so as to sequentially conduct the initialization processing one by one.
Specifically, since most of the color image processing apparatuses and most of the color image forming apparatuses are provided with hardware devices being equivalent for every primary color, the processing velocity of such the apparatus has been improved by employing the simultaneous and parallel processing as abovementioned. In this connection, with respect to this kind of processing, Tokkohei 2-22377 (Japanese Patent Publication) sets forth a proposal in regard to an efficient processing method.
According to the prior art technology set forth in Tokkohei 2-22377, a different CPU is allotted to the operating section side in order to improve the responsivity. Concretely speaking, according to the invention set forth in Tokkohei 2-22377, various kinds of control CPUs, being different from each other in the heterogeneous multi core environment, are made to have separate roles, such as a controlling CPU, a managing CPU, etc., so as to smoothly implement various kinds of operations.
By employing the abovementioned technology, although it becomes possible to improve the responsivity, there have arisen other problems that the cost of the total system has increased, the communication controlling operation in conjunction with the total system has become necessary, etc. For instance, in the system in which the SMP-type (Symmetrical Multi-Processing type) OS is installed, the processing capability is improved by automatically allotting a plurality of thread processes to the cores being in midcourse of idling. When the abovementioned SMP-type OS is employed, a single OS is developed into a common memory of CPU cores, so as to allot various kinds of processing, such as application software, etc., to the plurality of CPU cores under the controlling operation of the single OS concerned.
Further, there has been employed such an OS that is provided with a hardware affinity mechanism to prevent the multi core CPU from generating deviations of dispatch timings in the real time processing environment, like that in the copier, and it is expected that the abovementioned OS will be increasingly utilized in this field.
However, in any one of the conventional apparatuses, such as an image forming apparatus, etc., no method for solving the aforementioned problems has existed so far and at present.